solprop.backends.numba_cpu#
The CPU backend: fused numba kernels over FFTW plans.
The execution chosen by a bake-off of candidate backends (docs/dev/backends.md
section 5): the seven numbered passes of architecture.md section 8 collapsed into a
handful of compiled kernels, the transforms planned once by FFTW on buffers that never
move, and all five thread pools owned rather than inherited.
solprop.backends.numba_cpu.kernels– the fused stage kernels, built from the per-element bodies ofsolprop.backends.bodies, which every backend shares.solprop.backends.numba_cpu.fft– the plans, the wisdom and the pools.solprop.backends.numba_cpu.backend– the seam and the stage driver.
Modules
The CPU backend: the seam, the stage driver and the statistics. |
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Execute CPU member stages with one compiled batch update and segmented norms. |
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The coupled flow of a coherent wall or a split block, on the CPU backend. |
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SEP 6's frequency-dependent electronic response on the fused node path. |
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SEP 6's frequency-dependent electronic response on the general modal route. |
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SEP 6's frequency-dependent electronic response on the Cartesian and planar routes. |
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Own compiled envelope-current workspaces and their forward transforms. |
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FFTW plans, wisdom, and the five thread pools the backend owns. |
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Own the held field-current streams, transforms and frequency assembly. |
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The general modal guide's nonlinear source, compiled, on the CPU backend. |
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The fused stage kernels: seven numbered passes in a handful of traversals. |
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The low-storage RK4IP march's register kernels and resident engine on |
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The fused Adams step's passes, compiled (SEP 14 phase 2, SEP 16 phase 3). |
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The pyFFTW import, made so that its OpenMP threads sleep when they are idle. |
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Opt-in wall-clock timers for the passes of a free-space evaluation (SEP 28 phase 0). |
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Execute the hybrid planar transform's compiled passes. |
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Execute separable spatial coefficients and bounded Cartesian column transfers. |
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Evaluate the reference z-table representation into persistent host stage arrays. |